As computers evolve, the speed of the Central Processing Unit (CPU) is increasing. Main memory associated with the CPU, sometimes referred to as Random Access Memory (RAM), has been architecturally changed to complement the increased CPU speed. The RAM has the advantage that it typically resides on the same printed circuit board (motherboard) as the CPU. Thus, interconnection between the CPU and RAM is not a limiting factor in achieving higher processing speeds.
An input/output (I/O) device, such as hard disk drive, usually are coupled to the motherboard through a bus system, a bridge circuit and cabling. The CPU and RAM are coupled to the bus system through another bridge circuit. Thus, the CPU or RAM must communicate with the I/O device through both bridges, the bus system and the cabling, naturally introducing a time delay in the communication.
One method of reducing the communication time delay is to couple the I/O device to the bus system with the least amount of hardware. One proposed technique has the I/O device coupled directly to the bus system, thereby eliminating at least the cabling. This "tightly-coupled" architecture reduces the communication time delay between the motherboard and the I/O device. With the increasing size of application programs and disk drive capacity, tightly coupling the I/O device to the bus system is an inexpensive alternative for providing increased processing speed.
Another method of reducing the communication time delay is to use a PCI (Peripheral Component Interconnect) Local Bus for the bus system. The PCI Local Bus is a known high performance 32- or 64-bit bus with multiplexed address and data lines. It is intended for use as an interconnect mechanism between highly integrated peripheral controller components, peripheral add-in boards, and processor/memory systems.
One limitation of the PCI Local Bus is that no more than ten electrical loads can be coupled thereto. Typical PCI Local Bus configurations are limited to six loads on the motherboard and two expansion connectors or slots, or two loads on the motherboard and four expansion connectors wherein each connector or slot on the PCI Local Bus is considered as one electrical load, and each device that is plugged into a connector is considered as an additional electrical load.
In addition, the actual stub or speedway length of the PCI Local Bus is limited to approximately five inches for bus operations at 33 MHz. In practical terms, present PCI-based implementations are thus limited to plug-in or expansion boards with usually no more than three or four boards per bus. This constraint is a function of the relatively fast clock frequency (up to 33 MHz or 66 MHz), fast-edge drivers and a low current rating of the output drivers.
However, many common peripheral I/O devices, such as CD-ROM, tape drives, floppy drives and hard disk drives, are not conveniently plugged into motherboard slots because the size and weight, and mounting and configuration requirements of the devices. Consequently, tightly coupled architecture is particularly applicable to PCI Local Bus system, yet the practical aspects of the implementation are not overcome.
One disadvantage of this architecture is that a disk drive will rock in a bus slot as the disk rotates. This rocking can weaken or break electrical contact between the traces of the disk drive and the slot. Eventually, communication with the disk drive will be error prone.
Another disadvantage of this architecture is that the weight of the disk drive, which is relatively heavy to other boards that are connected to the bus system, may damage the expansion slot. This problem is worsened when the rocking occurs.
Therefore, an need exists for a support for a hard drive assembly coupled to an internal slot of a computer. Such a support will enable a hard disk drive to be tightly coupled to a bus system slot while maintaining proper electrical contact.